The invention relates to a circuit arrangement for detection of an erroneous selection signal supplied to a selection means.
In a conventional circuit arrangement of this type, an erroneous selection signal supplied to a selection circuit can be detected by adding a parity bit to a selection signal at a selection signal generating circuit and conducting a parity check for the selection signal by a parity check circuit provided on the input side of the selection circuit.
However, such a conventional circuit arrangement has a disadvantage that when a fault occurs at any of the selection signal generating circuit and the parity check circuit, error detection of selection signals is not properly performed.